1. Technical Field
The present invention relates in general to the field of computers, and in particular to the testing of circuits, including integrated circuits. Still more particularly, the present invention relates to a method and system for locating a defect in a scan chain.
2. Description of the Related Art
A significant expense incurred during the manufacture of integrated circuit (IC) wafers is testing. Such testing generally entails inputting data into a logic circuit on the wafer at a first test access point, and then reading the output results at a second test access point. Often, finer granularity is required to determine whether the logic is functioning properly. That is, a known input data into a logic circuit may result in a desired (expected) output, but the desired output may be the result of multiple offsetting errors. For example, if a “1” is input into three inverters in series, a “0” will be output whether all three inverters are working properly or if only one of the inverters is functioning and the other two are straight shorts. To determine whether the complete logic circuit is functioning properly, data is read out at intermediate logic levels using scan chains, which allow probes to pull off intermediary ults from the logic circuit.
Referring to FIG. 1, there is depicted a prior art scan chain 100, which includes combinational logic blocks 102a, 102b, and 102c, which represent combinational logic that executes various predetermined logic functions. The combinational logic blocks are interconnected by a scan chain latch circuit 104a, which interconnects combinational logic blocks 102a and 102b, and scan chain latch circuit 104b which interconnects combinational logic blocks 102b and 102c. 
Data is written to the combinational logic blocks 102a, 102b, and 102c in a parallel or broadside manner via respective primary input (PI) vectors 106a, 106b, 106c. Data is read from the combinational logic blocks 102a, 102b, 102c in a parallel fashion to the primary output (PO) vectors 108a, 108b, 108c, respectively. The PO vectors 108a, 108b function as PI vectors to respective scan chain latch circuits 104a and 104b. 
The scan chain latch circuits 104a and 104b may also be loaded serially to enable testing of the scan chain latches 104a and 104b. In particular, shift register input (SRI) line 120 provides a serial input to scan chain latch 104a. Similarly, shift register output (SRO) line 122 provides an output from scan chain latch 104b. Scan chain latches 104a and 104b are interconnected by serial line 124. Serial line 124 functions as a SRO for scan chain latch 104a and as an SRI for scan chain latch 104b. One or a plurality of system clocks 126 output timing signals to control timing operations of the combinational logic blocks 102 and scan chain latches 104. One or a plurality of scan chain clocks 128 provide timing signals to scan chain latches 104.
While scan chains are useful in determining whether a logic circuit is functioning properly, the scan chains themselves may also be defective. While such defects may be from defective latches in the scan chain, if the latches are robust (designed to ensure their integrity), then defects are primarily in the wiring connecting the latches. Such defects may be opens (a clean break in the wiring), shorts (the wiring touching another wire inadvertently), or stuck-at faults (the wiring touching either ground or voltage). The most problematic wiring defect is a stuck-at fault, since the latch otherwise appears to be functioning properly, albeit with a constant input value. That is, if a connector going into the input of the latch is shorted to ground, then that latch will only be able to latch a logical zero. Likewise, if the input is shorted to voltage, then that latch will only be able to latch a logical one.
Therefore, it would be beneficial to have a method and system that could locate exactly where in the scan chain the connector defect occurred. By finding the exact location of the defect, a more precise manufacture solution for correcting the defect can be determined for the defective scan chain, as well as the overall wiring layer of the IC. Preferably, such an method and system would detect the location of multiple connector defects.